1. Field of the Invention
This invention relates generally to semiconductor manufacturing, and, more particularly, to a method and apparatus for electrically measuring insulating film thickness, such as the width of sidewall spacers.
2. Description of the Related Art
The technology explosion in the manufacturing industry has resulted in many new and innovative manufacturing processes. Today""s manufacturing processes, particularly semiconductor manufacturing processes, call for a large number of important steps. These process steps are usually vital, and therefore, require a number of inputs that are generally fine-tuned to maintain proper manufacturing control.
The manufacture of semiconductor devices requires a number of discrete process steps to create a packaged semiconductor device from raw semiconductor material. The various processes, from the initial growth of the semiconductor material, the slicing of the semiconductor crystal into individual wafers, the fabrication stages (etching, doping, ion implanting, or the like), to the packaging and final testing of the completed device, are so different from one another and specialized that the processes may be performed in different manufacturing locations that contain different control schemes.
Generally, a set of processing steps is performed on a group of semiconductor wafers, sometimes referred to as a lot, using a semiconductor-manufacturing tool called an exposure tool or a stepper. As an example, an etch process may be performed on the semiconductor wafers to shape objects on the semiconductor wafer, such as polysilicon lines, each of which may function as a gate electrode for a transistor. As another example, a plurality of metal lines, e.g., aluminum or copper, may be formed that serve as conductive lines that connect one conductive region on the semiconductor wafer to another. The manufacturing tools communicate with a manufacturing framework or a network of processing modules. Each manufacturing tool is generally connected to an equipment interface. The equipment interface is connected to a machine interface to which a manufacturing network is connected, thereby facilitating communications between the manufacturing tool and the manufacturing framework. The machine interface can generally be part of an advanced process control (APC) system. The APC system initiates a control script, which can be a software program that automatically retrieves the data needed to execute a manufacturing process.
FIG. 1 illustrates a typical wafer 100 comprising a semiconductor 105. The wafer 100 typically includes a plurality of individual semiconductor die 150 arranged in a grid, with spaces, called scribe lines, 155 between individual ones of the semiconductor die 150. Photolithography steps are typically performed by a stepper on approximately one to four die locations at a time, depending on the specific photomask employed. Photolithography steps are generally performed to form patterned layers of photoresist above one or more process layers that are to be patterned. The patterned photoresist layer can be used as a mask during etching processes, wet or dry, performed on the underlying layer or layers of material, e.g., a layer of polysilicon, metal or insulating material, to transfer the desired pattern to the underlying layer. The patterned layer of photoresist is comprised of a plurality of features, e.g., line-type features, such as a polysilicon line, or opening-type features, that are to be replicated in an underlying process layer. The wafer 100 may typically have one or more indicia for alignment purposes, such as a notch 110 and/or registration marks 115.
Turning now to FIG. 2A, various features 200A that may be associated with any one of the semiconductor die 150 are shown. As noted above, the fabrication stages may include doping a source region 205 and a drain region 210 in a semiconductor substrate of the wafer 100. A gate region 220 may also be created on or in the semiconductor substrate. The gate region 220 has associated with it a length (LGATE) 225. Also associated with the gate region 220 is an effective gate length (LEFF) 230. The effective gate length 230 corresponds to the distance between the source region 205 and the drain region 210 in which the gate region 220 is present.
Using the features 200A and associated characteristics of FIG. 2A, optimizations designed to increase circuit speed are discussed. Three parameters for circuit speed are the gate capacitance, the transistor drive current, and the transistor leakage current. The gate capacitance is proportional to the gate length 225. That is, for a larger gate length 225 the gate capacitance is higher. The transistor drive current is inversely proportional to the effective gate length 230. That is, for a smaller effective gate length 230 the transistor drive current is higher. The transistor leakage current is also inversely proportional to the effective gate length 230. That is, for a smaller effective gate length 230 the transistor leakage current is higher. While a larger transistor drive current may be preferred, a smaller transistor leakage current is preferred.
The delay, xcfx84, for a given transistor must be low for the overall circuit speed to be optimized. The delay is proportional to the gate capacitance (C) and the gate voltage (V) and inversely proportional to the drive current (Idrive).   τ  =      CV          I      drive      
Optimizing for circuit speed calls for controlling the effective gate length 230 while making the gate length 225 small. As a smaller gate length 225 leads to a smaller gate capacitance, for the same drive current, the delay is low. The semiconductor industry has looked for ways to accomplish this goal.
Turning to FIG. 2B, one way to achieve the goal above is to use sidewall spacers 250, a type of insulating film, in an attempt to limit leakage current. Various improved features 200B that may be associated with any one of the semiconductor die 150 are shown. As noted above, the fabrication stages may include doping the source region, shown as a source region 205A before the sidewall spacers are formed and a source region 205B after the sidewall spacers are formed. Likewise, the fabrication stages may include doping the drain region, shown as a drain region 210A before the sidewall spacers are formed and doping a drain region 210B after the sidewall spacers are formed. The gate region 220 is also shown with its associated length (LGATE) 225. Also associated with the gate region 220 are an old effective gate length 230A before the sidewall spacers and a new effective gate length 230B after the sidewall spacers.
The sidewall spacers 250 provide an increased effective gate length 230 for a given gate length 225. Put another way, for an effective gate length 230, the given gate length 225 can be made smaller. When using sidewall spacers 250, the width of the sidewall spacers 250 must be monitored closely if the performance of the finished circuit is to be predicted with any confidence. One aspect of the present invention is directed to monitoring the width of insulating films, at least in part, using the sidewall spacers as an illustrative example.
In one aspect of the present invention, a method is provided for measuring insulating film thickness, such as the width of sidewall spacers. The method includes positioning a first test structure having a first resistance at a first location on a semiconductor wafer and positioning a second test structure having a second resistance different from the first resistance at a second location on the semiconductor wafer. The method also includes measuring the first resistance of the first test structure and measuring the second resistance of the second test structure. The method also includes determining an average characteristic of the first test structure and the second test structure, other than resistance, based on the first resistance of the first test structure and the second resistance of the second test structure.
In another aspect of the present invention, an apparatus is provided. The apparatus includes a semiconductor substrate, a first test structure integrated into the semiconductor substrate, and a second test structure integrated into the semiconductor substrate. The first test structure includes a first highly doped region, a first gate region and a second gate region separated by at least a portion of the first highly doped region, a first insulating layer adjacent to the first gate region towards the second gate region, and a second insulating layer adjacent to the second gate region towards the first gate region. The first insulating layer and the second insulating layer are separated by a first non-zero distance. The second test structure includes a second highly doped region, a third gate region and a fourth gate region separated by at least a portion of the second highly doped region, a third insulating layer adjacent to the third gate region towards the fourth gate region, and a fourth insulating layer adjacent to the fourth gate region towards the third gate region. The third insulating layer and the fourth insulating layer are separated by a second non-zero distance different from the first non-zero distance. The first test structure and the second test structure are configured for determination of the average thickness of insulating layers through measuring a first resistance between the first highly doped region and a first adjacent highly doped region that is also proximate with the first gate region and the second gate region and measuring a second resistance between the second highly doped region and a second adjacent highly doped region that is also proximate with the third gate region and the fourth gate region.
In still another aspect of the present invention, a system of automatic process control measuring insulating film thickness, such as the width of sidewall spacers, to monitor the process stream and possibly modify the process stream. The system includes a computer system, a manufacturing model coupled with the computer system, a machine interface coupled with the manufacturing model, a processing tool configured to process semiconductor wafers and coupled to receive at least one control input parameter signal from the machine interface, and a metrology tool coupled with the first processing tool and the second processing tool. The manufacturing model is configured to generate and modify at least one control input parameter. The machine interface is configured to receive process recipes from the manufacturing model. The metrology tool is configured to acquire metrology data. The metrology data includes a resistance from each test structure associated with a semiconductor wafer. The metrology tool is configured to provide the resistance to the computer system to determine an average characteristic of a parameter other than resistance of the semiconductor wafer.